geometry process details principal device types cbcp69 cbcx69 czt751 mps750 mps751 gross die per 5 inch wafer 10,583 process CP714V small signal transistor pnp - high current transistor chip process epitaxial planar die size 40 x 40 mils die thickness 7.0 mils base bonding pad area 7.9 x 8.7 mils emitter bonding pad area 9.0 x 14 mils top side metalization al - 30,000? back side metalization au - 18,000? www.centralsemi.com r0 (17-november 2010)
process CP714V typical electrical characteristics www.centralsemi.com r0 (17-november 2010)
|